1. Field of the Invention
The invention pertains to an integrated memory circuit having memory array cells (e.g., nonvolatile memory cells), which normally reads the cells in a mode in which an internally-generated reference current is provided to (or sunk from) one or more sense amplifiers, but which alternatively operates in a test mode in which an external device sources or sinks a selected external reference current which flows through an external pad to or from the sense amplifiers. The integrated circuit of the invention includes circuitry which operates in a test mode to allow any of a wide range of sense amplifier reference currents to flow through an external pad between at least one sense amplifier and an external device connected to the pad.
2. Description of Related Art
Throughout the specification, including in the claims, the terms "connects" and "connected" are used (in the context that an electronic component is "connected" to another electronic component or "connects" one circuit element to another) in a broad sense to denote that the components are electrically or electromagnetically coupled with sufficient strength under the circumstances. It is not used in a narrow sense requiring that an electrically conducting element is physically connected between the two components.
Nonvolatile memory chips (integrated circuits) with higher density are being introduced to the market each day. In order to achieve higher density, chip manufacturers must continually decrease the size of elements of the chips (such as the size of each cell of a memory array implemented in each chip). With memory array cells having submicron feature sizes, the slightest change in processing of one memory cell relative to another during manufacture results in a big difference in the behavior of the cells with respect to each other.
Many conventional memory chips operate in either a test mode in which input/output ("I/O") pads are connected directly to an array of memory cells, or in a "normal" (or "active") mode in which the I/O pads are connected through buffer circuitry to the array of memory cells. In the latter mode (the "normal" mode) the chip can perform read/write operations in which data is written to selected ones of the cells through an input buffer (or data is read from selected ones of the cells through an output buffer).
FIG. 1 is a simplified block diagram of a conventional memory chip of this type. Memory chip 3 of FIG. 1 includes at least one I/O pad 30 (for asserting output data to an external device or receiving input data from an external device), input/output buffer circuit 10 for I/O pad 30, test mode switch M1, address buffers A0 through Ap for receiving memory address bits from an external device, row decoder circuit (X address decoder) 12, column multiplexer circuit (Y multiplexer) 14, memory array 16 (comprising columns of nonvolatile memory cells, such as column 16A), pad 90, switch 121 connected between pad 90 and other components of chip 3, and control unit 29. Each of the cells is preferably a flash memory device, for example of the type described with reference to FIG. 2. Each of address buffers A0 through Ap includes an address bit pad for receiving (from an external device) a different one of address bit signals X0 through Xn and Y0 through Ym.
I/O buffer circuit 10 includes a "write" branch and a "read" branch." The write branch comprises input buffer 18. The read branch comprises sense amplifier 19 and output buffer 20.
In the normal operating mode of chip 3 of FIG. 1, control unit 29 can cause chip 3 to execute a write operation in which it receives data (to be written to memory array 16) from an external device at I/O pad 30, buffers the data in the write branch, and then writes the data to the appropriate memory cell. In this normal operating mode, control unit 29 can also cause chip 3 to execute a read operation in which it amplifies and buffers data (that has been read from array 16) in the read branch, and then asserts this data to I/O pad 30.
Although only one I/O pad (pad 30) is shown in FIG. 1, typical implementations of the FIG. 1 circuit include a plurality of I/O pads, and each I/O pad is buffered by an I/O buffer circuit similar or identical to circuit 10. For example, one implementation of the FIG. 1 circuit includes eight I/O pads, eight buffer circuits identical to circuit 10, one line connected between the output of the output buffer 20 of each buffer circuit and one of the I/O pads (so that eight data bits can be read in parallel from buffers 20 to the pads), and one line connected between the input of the input buffer 18 of each buffer circuit and one of the I/O pads (so that eight data bits can be written in parallel from the pads to buffers 18). Each I/O pad (including I/O pad 30) typically has high impedance when the output buffer is not enabled.
Each of the cells (storage locations) of memory array circuit 16 is indexed by a row index (an "X" index determined by decoder circuit 12) and a column index (a "Y" index output determined by circuit 14). FIG. 2 is a simplified schematic diagram of two columns of cells of memory array 16 (with one column, e.g., the column on the right, corresponding to column 16A of FIG. 1). The column on the left side of FIG. 2 comprises "n" memory cells, each cell implemented by one of floating-gate N-channel transistors N1, N3, . . . , Nn. The drain of each of transistors N1-Nn is connected to bitline 13, and the gate of each is connected to a different wordline (a different one of wordline 0 through wordline n). The column on the right side of FIG. 2 also comprises "n" memory cells, each cell implemented by one of floating-gate N-channel transistors N2, N4, . . . , Nm. The drain of each of transistors N2-Nm is connected to bitline 15, and the gate of each is connected to a different wordline (a different one of wordline 0 through wordline n). The source of each of transistors N1, N3, . . . , Nn, and N2, N4, . . . , Nm is held at a source potential (which is usually ground potential for the chip during a read or programming operation).
Each memory cell is a nonvolatile memory cell since each of transistors N1, N3, . . . , Nn, and N2, N4, . . . , Nm has a floating gate capable of semipermanent charge storage. The current drawn by each cell (i.e., by each of transistors N1, N3, . . . , Nn, and N2, N4, . . . , Nm) depends on the amount of charge stored on the cell's floating gate. Thus, the charge stored on each floating gate determines a data value that is stored "semipermanently" in the corresponding cell. In cases in which each of transistors N1, N3, . . . , Nn, N2, N4, . . . , and Nm is a flash memory device (as indicated in FIG. 2 by the symbol employed to denote each of transistors N1, N3, . . . , Nn, N2, N4, . . . , and Nm), the charge stored on the floating gate of each is erasable (and thus the data value stored by each cell is erasable) by appropriately changing the voltage applied to the gate and source (in a well known manner).
The manner in which sense amplifier 19 (shown in FIG. 1 and shown directly connected to bitline 13 in FIG. 2) is employed to read each cell connected along bitline 13 will next be described.
In response to address bits Y0-Ym, Y multiplexer circuit 14 (of FIG. 1) determines a column address which selects one of the columns of cells of array 16 (connecting the bitline of the selected column to Node 1 of FIG. 1), and in response to address bits X0-Xn, decoder circuit 12 (of FIG. 1) determines a row address which selects one cell in the selected column. Consider an example in which the column address selects the column on the left side of FIG. 2 (the column including bitline 13) and the row address selects the cell connected along wordline 0 (the cell comprising transistor N1). To read the data value stored in the selected cell, a signal (a current signal) indicative of such value is provided from the cell's drain (the drain of transistor N1, in the example), through bitline 13 and circuit 14, to Node 1 of FIG. 1 (which is the noninverting input of sense amplifier 19 as shown in FIG. 2). To write a data value to the selected cell, a signal indicative of such value is provided to the cell's gate and drain (the gate and drain of transistor N1, in the example). The reference input terminal of sense amplifier 19 (which is the inverting input terminal in FIG. 1) is held at reference voltage V.sub.REF by circuitry (not shown in FIG. 1) which is part of chip 3. An example of such internal reference voltage supply circuitry is that of FIG. 5 of U.S. patent application Ser. No. 08/508,923 entitled "Memory System Having Non-volatile Data Storage Structure for Memory Control Parameters and Method," filed by F. Roohparvar on Jul. 28, 1995 (assigned to the assignee of the present application).
When reading the selected cell, if the cell is in an erased state, the cell will conduct a first current which is converted to a first voltage in sense amplifier 19. If the cell is in a programmed state, it will conduct a second current which is converted to a second voltage in sense amplifier 19. Sense amplifier 19 determines the state of the cell (i.e., whether it is programmed or erased corresponding to a binary value of 0 or 1, respectively) by comparing the voltage indicative of the cell state to reference voltage V.sub.REF. The outcome of this comparison is an output which is either high or low (corresponding to a digital value of one or zero) which sense amplifier 19 sends to output buffer 20. Output buffer 20 in turn asserts a corresponding data signal to I/O pad 30 (from which it can be accessed by an external device).
Sense amplifier 19 can be employed in various memory operations, including verification operations (each of which is part of an erase or programming operation) for verifying the programmed or erased state of cells of a memory array, and read operations (which are not part of an erase of programming operation). In all of these operations, the sense amplifier develops a voltage which is indicative of current flow through a cell being sensed, and the sense amplifier compares this sensed voltage to reference voltage V.sub.REF. Typically, the reference voltage V.sub.REF has one value in read operations and program verify operations and another value in erase verification operations.
For example, sense amplifier 19 of FIG. 2 (whose noninverting input terminal is connected to bitline 13) can be used to verify the state of flash memory cell N1 of FIG. 2 as part of an attempt to erase this cell. To do so, the other cells connected to bitline 13 are deselected and a voltage (e.g., +5.5 volts) is applied to cell N1's wordline. If the wordline voltage exceeds the erased threshold voltage, cell N1 conducts a cell current (which flows from a node held at drain voltage V.sub.D through load 13A connected along bitline 13, and from the drain to the source of cell N1). This cell current is indicative of the erased threshold voltage of the cell, with such current causing a drop in voltage at the noninverting input terminal of sense amplifier 19 (below the voltage that would exist in the absence of cell current). If the voltage at the noninverting input terminal of sense amplifier 19 drops below the reference voltage V.sub.REF provided at the reference input terminal (inverting input terminal) of sense amplifier 19, the output of sense amplifier 19 goes low (which is normally interpreted to indicate that the cell has been adequately erased). Otherwise, the output of sense amplifier 19 is high, which is normally interpreted to indicate that the cell has not been adequately erased.
With reference again to FIG. 1, the function of switch M1 is to switch the FIG. 1 chip between its test mode and its normal operating mode. Conventionally, switch M1 is an NMOS transistor whose gate receives a control signal ("Test Mode Enable") from internal control logic within control unit 29. The source and drain of M1 are connected in series with I/O pad 30 and circuit 14. Switch M1 operates as follows in response to the control signal:
M1 is "on" when Test Mode Enable is high (when the value of Test Mode Enable triggers the "test" mode of FIG. 1), and thus M1 functions as a pass transistor which passes a signal (a "test" signal) indicative of test data to be written to or read from a selected cell of array 16 (e.g., a current signal indicative of test data read from the selected cell) between its source and drain (and thus between I/O pad 30 and the selected cell of array 16). If buffers 18 and 20 of circuit 10 are disabled when M1 is on, the test signals pass through M1 but not through circuit 10; and
M1 is "off" when Test Mode Enable is low (when the value of Test Mode Enable triggers the "normal" operating mode of FIG. 1), so that signals (indicative of data to be written to array 16) provided from an external device to I/O pad 30 are buffered in input buffer 18 and then asserted to array 16, or signals (indicative of data read from array 16) are asserted from array 16 to sense amplifier 19, and the output of sense amplifier 19 is buffered in output buffer 20 and asserted to I/O pad 30. Typically, the "low" value of Test Mode Enable is ground potential.
In the normal operating mode of FIG. 1 (with M1 "off"), the FIG. 1 circuit executes a write operation as follows. Each of address buffers A0 through An asserts one of bits X0-Xn to decoder circuit 12, and each of address buffers An+1 through Ap asserts one of bits Y0-Ym to circuit 14. In response to these address bits, circuit 14 determines a column address (which selects one of the columns of memory cells of array 16, such as column 16A), and circuit 12 determines a row address (which selects one cell in the selected column). In response to a write command supplied from control unit 29, a signal (indicative of data) present at the output of input buffer 18 (which has been enabled by the appropriate level of the control signal "DATA DRIVER ON") is asserted through circuit 14 to the cell of array 16 determined by the row and column address (e.g., to the drain of such cell). During such write operation, output buffer 20 is disabled (in response to an appropriate level of control signal OUTPUT ENABLE).
A data latch (not shown in FIG. 1) is typically provided between input buffer 18 and I/O pad 30 for storing data (to be written to a memory cell) received from I/O pad 30. When the latched data is sent to input buffer 18, buffer 18 produces a voltage at Node 1 which is applied to the selected memory cell. Input buffer 18 is typically implemented as a tri-statable driver having an output which can be placed in a high impedance mode (and thus disabled) during a read operation. Input buffer 18 is disabled by asserting (to input buffer 18) an appropriate level of the control signal DATA DRIVER ON. In some implementations, the functions of the latch and input buffer 18 are combined into a single device.
In the normal operating mode (with M1 "off"), the FIG. 1 circuit executes a read operation as follows. Each of address buffers A0 through An asserts one of bits X0-Xn to address decoder circuit 12, and each of address buffers An+1 through Ap asserts one of bits Y0-Ym to circuit 14. In response to these address bits, circuit 14 asserts a column address to memory array 16 (which selects one of the columns of memory cells, such as column 16A), and circuit 12 asserts a row address to memory array 16 (which selects one cell in the selected column). In response to a read command supplied from control unit 29, a current signal indicative of a data value stored in the cell of array 16 (a "data signal") determined by the row and column address is supplied from the drain of the selected cell through the bitline of the selected cell and then through circuit 14 to sense amplifier 19. The output of sense amplifier 19 is buffered in output buffer 20 (which is enabled by an appropriate level of control signal "OUTPUT ENABLE") and finally asserted at I/O pad 30. During such read operation, input buffer 18 is disabled (in response to an appropriate level of control signal DATA DRIVER ON).
Chip 3 of FIG. 1 also includes a pad 90 which receives a high voltage V.sub.pp from an external device, and a switch 121 connected to pad 90. During some steps of a typical erase or program sequence (in which the cells of array 16 are erased or programmed), control unit 29 sends a control signal to switch 121 to cause switch 121 to close and thereby assert high voltage V.sub.pp to various components of the chip including X decoder 12. Voltage V.sub.pp is higher (typically V.sub.pp =12 volts) than the normal operating mode supply voltage (typically V.sub.cc =5 volts or V.sub.cc =5.5 volts) for the MOS transistors of chip 3.
During the test mode, input buffer 18, sense amplifier 19, and output buffer 20 are all disabled (in response to appropriate levels of their respective control signals DATA DRIVER ON, SENSE AMPLIFIER ENABLE, and OUTPUT ENABLE, which are generated by control unit 29).
During a write operation in the normal operating mode, control signal SENSE AMPLIFIER ENABLE disables sense amplifier 19. During a read operation in the normal operating mode, circuit 14 is employed to access the desired cell in array 16 and control signal SENSE AMPLIFIER ENABLE enables sense amplifier 19 so that sense amplifier 19 can determine the state of the selected cell as described.
FIG. 3 is a block diagram of a conventional flash memory chip 103 which is a variation on memory chip 3 of FIG. 1 and which performs essentially all the same functions as does chip 3. The components of flash memory system 103 which correspond to components of memory chip 3 of FIG. 1 are identified by the same reference numerals as in FIG. 1. Memory array 16 of system 103 consists of flash memory cells arranged in rows and columns with a total of 256K of eight bit words in the array. The individual cells (not depicted) are addressed by eighteen address bits (A0-A17), with nine bits being used by X decoder circuit 12 to select the row of array 16 in which the target cell is located and the remaining nine bits being used by Y decoder circuit 14A (of Y-multiplexer 14) to select the appropriate column of array 16. Each target cell is read using a sense amplifier and associated components represented by block 33. Block 33 can include one sense amplifier (which can be coupled to any column selected by Y-multiplexer 14, or several sense amplifiers (each of which can be coupled to a selected column of a different subset of the columns of array 16). Each sense amplifier can be identical to sense amplifier 19 of above-discussed FIG. 1 or below-discussed FIG. 4.
Internal state machine 120 of control unit 29 of chip 103 controls detailed operations of chip 103 such as the various individual steps necessary for carrying out programming, reading and erasing operations. State machine 120 thus functions to reduce the overhead required of the processor (not depicted) typically used in association with chip 103.
If memory array 16 is to be erased (typically, all or large blocks of cells are erased at the same time), the processor must cause the Output Enable OE pin to be inactive (high), and the Chip Enable CE and Write Enable WE pins to be active (low). The processor can then issue an 8 bit command 20H (0010 0000) on data I/O pins DQ0-DQ7, typically called an Erase Setup command (one of I/O pins DQ0-DQ7 corresponds to I/O pad 30 of FIG. 1). This is followed by issuance of a second eight bit command D0H (1101 0000), typically called an Erase Confirm command. Two separate commands are used so as to minimize the possibility of an inadvertent erase operation.
The commands are transferred to data input buffer 122 (input buffer 18 of FIG. 1 corresponds to a component of buffer 122 which receives one bit of each command) and the commands are then transferred to command execution logic unit 124 of control unit 29. Logic unit 124 then instructs state machine 120 to perform all of the numerous and well known steps for erasing array 16.
During some steps of a typical erase sequence, state machine 120 sends a control signal to switch 121, to cause switch 121 to close and thereby assert a high voltage V.sub.pp to various components of chip 103, including X decoder 12 and Y multiplexer 14. As in chip 3 of FIG. 1, voltage V.sub.pp is typically received by chip 103 from an external device at a power supply pad of chip 103 connected to switch 121 (e.g., pad 90 shown in FIG. 1). Voltage V.sub.pp is higher (typically V.sub.pp =12 volts) than the normal operating mode supply voltage (typically V.sub.cc =5 volts or V.sub.cc =5.5 volts) for the MOS transistors of chip 103.
Once the erase sequence is completed, state machine 120 updates an 8 bit status register 126, the contents of which are transferred to data output buffer 128 which is connected to data I/O pins DQ0-DQ7 of the memory system (output buffer 18 of FIG. 1 corresponds to a component of buffer 128 which receives one bit from register 126). The processor periodically polls the data I/O pins to read the contents of status register 126 in order to determine whether the erase sequence has been completed and whether it has been completed successfully.
Chip 103 of FIG. 3 (and chip 3 of FIG. 1) typically implements a complicated sequence of steps to erase all or selected ones of the cells of array 16 (so that they store data indicative of a logical "1") or to program all or selected ones of such cells (so that they store data indicative of a logical "0"). These steps typically include verification steps for verifying the status of all or selected ones of the cells at various stages of an erase (or programming) operation.
During a typical erase operation, it is desired to erase all the cells of array 16 so that the threshold voltages are all within a specified voltage range. That range is typically a small positive voltage range such as from +1.5 to +3.0 volts. If the erased cells fall within this range, the cell to be read (the "selected" or "target") cell will produce a cell current in a read operation. The presence of cell current flow indicates that the cell is in an erased state (logic "1") rather than a programmed state (logic "0"). Cell current is produced in a selected erased cell if the voltage applied to the control gate of the cell, by way of the wordline connected to X decoder 12, exceeds the threshold voltage of the erased cell. In addition, cells which are not being read ("deselected" cells) are prevented from producing a cell current even if such cells have been erased to a low threshold voltage state. By way of example, for cells located in the same row as the selected cell, by definition, share the same wordline as the selected cell. However, the drains of the deselected cells will be floating thereby preventing a cell current from being generated. Deselected cells in the same column will not conduct cell current because the wordlines of such deselected cells are typically grounded. Thus, the gate-source voltage of these cells will be insufficient to turn on these deselected cells even if they are in an erased state.
After an erase operation, the vast majority of cells will have a proper erased threshold voltage. However, it is possible that a few (or even one) of the cells may have responded differently to the erase sequence and such cell(s) have become overerased. If a cell is overerased, the net charge on its floating gate is positive. The result will be that the threshold voltage will be negative to some extent. Thus, when such overerased cell is deselected (the wordline connected to the overerased deselected cell is grounded), the deselected cell will nevertheless conduct current. This current will interfere with the reading of the selected cell thereby preventing proper memory operation.
It is necessary to perform a complicated sequence of steps to erase or program the cells of a conventional nonvolatile memory chip because the individual cells of each array of such a chip typically behave differently, and thus the chip's state machine needs to ensure that all cells have at least a minimum margin at the end of each erase (or program) operation. This, however, does not mean that all the cells will be left with the same threshold voltage (V.sub.th) at the end of an erase or program operation. For example, if during programming of all cells of an array, the state machine sets the minimum V.sub.th of all programmed cells to 5.5 volts, there may be many cells that have been programmed to a V.sub.th in the range from 7 to 7.5 volts at the end of the programming operation. So, there is a range of V.sub.th s for the programmed cells. The same is true for an erase operation, and thus there is typically a range of V.sub.th s for the erased cells. The V.sub.th range for erased cells may typically be from 1 volt to 3 volts after an erase operation, if the maximum V.sub.th of an erased bit is set to 3 volts by the state machine.
Measuring the V.sub.th distribution of the cells of an array (after erase and program operations) is of great importance to memory manufacturers and designers. The degree of tightness of such distribution is a good indicator of how well the memory elements have been processed (e.g., during manufacture of the chip) and how well the state machine is functioning.
The threshold voltages ("V.sub.th s") of nonvolatile cells of a memory array have conventionally been measured indirectly (during a test mode) by measuring current/voltage ("I/V") characteristics of the cells for a sequence of different voltages between the source and drain of each cell and then deriving the V.sub.th values from the measured I/V characteristics. For example, in a conventional test mode implemented by the FIG. 1 chip, a selected cell of array 16 is connected directly to I/O pad 30 (or to several I/O pads including I/O pad 30), and a current/voltage characterization is performed on the selected cell as follows. The voltage at the cell's drain (the potential at which bitline 15 of FIG. 2 is held, for example) is controllable since the selected bitline is directly connected to an external device through I/O pad 30, and the external device varies the voltage at which the bitline (bitline 15, in the example) is held. By sweeping the voltage on I/O pad 30 during the test mode and monitoring the resulting cell current (the current flowing from the selected cell's drain through bitline 15, circuit 14, Node 1, and switch M1 to I/O pad 30, in the example), an I/V curve for the cell is obtained. This process is repeated for each of a sequence of gate voltages to obtain a family of I/V curves for the cell, and the family of I/V curves is analyzed to determine the cell's threshold voltage.
There are several serious problems with (and limitations of) conventional methods (such as the method described in the previous paragraph) and conventional apparatus for test mode measurement of I/V curves for selected cells. One such problem is that the tester must arbitrarily assign a current value which characterizes a cell as an "erased" or "programmed" cell when analyzing the measured I/V curves. However, this arbitrarily assigned value is not necessarily the reference current value employed in the sense amplifier to determine the state of each cell during normal (non-test mode) chip operation. Thus, even though a cell is arbitrarily identified by the tester as a "programmed" cell (as a result of test mode operation of the chip), the sense amplifier may be able to read the cell as an erased cell (during normal operation of the chip).
Another of such problems is that measurement of cell current (in a conventional test mode) must be done through the measurement unit of the tester. Thus, the operations of switching from cell address to cell address and making the measurement for each cell consumes a very long time per byte. For a four megabyte or larger cell array, the amount of time required for measuring all the cells is very long, and the tester does not usually have the capability to make decisions regarding passage or failure of bits based on continuous I/V measurement.
U.S. patent application Ser. No. 08/511,614, filed Aug. 4, 1995 (assigned to the assignee of the present application), discloses a method and apparatus intended to overcome problems of conventional measurement of the threshold voltage (V.sub.th) of cells of a memory chip. U.S. Ser. No. 08/511,614 teaches applying a sequence of selected voltages directly to wordlines of a flash memory cell array (and thus to the gates of all or selected ones of the rows of cells); in response to application of each selected voltage, employing the chip's read circuitry (including the sense amplifier and other circuitry employed to execute a read operation in the chip's normal operating mode) to read the cells connected along each wordline; and identifying which of the cells are read by the read circuitry as being in their intended (erased or programmed) state and which of them are not read as being in their intended state. By implementing such direct (or "true") V.sub.th measurements, the threshold voltage of each cell is rapidly and directly measured.
U.S. Ser. No. 08/511,614 discloses a switch which enables application of a wide range of voltages from an external device to the wordlines of the chip's memory array for measuring a full range of typical V.sub.th values for erased and programmed cells of the array. Use of this switch eliminates the following problem with a memory chip having conventional test mode circuitry (such as that of FIG. 1). In such a conventional chip, wordlines are accessed through PMOS transistors formed in a well in a row address decoder circuit (e.g., X decoder 12 of FIG. 1). The supply voltage for such PMOS transistors (denoted as V.sub.cc in FIG. 1) is typically equal to 5 volts or 5.5 volts. If an attempt were made to decrease a "wordline voltage" (a voltage to be applied to a wordline through the decoder) from V.sub.cc to a selected value less than (V.sub.cc -V.sub.t), where V.sub.t is the threshold voltage (typically less than 1 volt) of the decoder's PMOS devices, the well would turn on and clamp the wordline voltage (thus preventing the wordline voltage from being further decreased to the selected value). This would prevent the wordline voltage from being decreased to values that are sufficiently low (e.g., values in the range from 1 volt to 3.5 volts) to measure the V.sub.th s of typical erased cells.
FIG. 4 is a block diagram of a memory chip 203 (of the type disclosed in U.S. Ser. No. 08/511,614) which includes improved switch 121' of the above-mentioned type (rather than switch 121 of FIG. 1). Switch 121' is connected to pad 90 for receiving a voltage V.sub.sup (supplied from an external device through pad 90) and the state of switch 121' is determined by control signals "VTH," "VTL," and "HV.sub.-- CYC" from control unit 29. Chip 203 also includes test mode switch 40 whose state is determined by control signal "Test Mode Enable 2" from control unit 29. Chip 203 is capable of operating in test modes in which X decoder 12' asserts the voltage V.sub.sup received from pad 90 to the control gates of cells of all or selected ones of the wordlines of array 16. Chip 203 can implement a true V.sub.th measurement test mode in which a sequence of different voltages V.sub.sup is applied to all or selected ones of the wordlines of array 16 (through switch 121' and X decoder 12') and the cells connected to such wordlines are read (using sense amplifier 19 and output buffer 20) once for each applied value of V.sub.sup. Chip 203 can also operate in other test modes in which a selected voltage V.sub.sup is applied (through switch 121' and X decoder 12') directly to wordlines of array 16 while another voltage is applied from an external pad (e.g., I/O pad 30) directly to the drain of one or more selected cells of array 16, in order to evaluate the voltage-current characteristics of those cells.
Test mode switch 40 of chip 203 can be identical to test mode switch M1 of FIG. 1, but is preferably implemented as one of the preferred test mode switches described (with reference to FIGS. 4 and 5) in U.S. patent application Ser. No. 08/508,848, entitled "Memory Circuit with Switch for Selectively Connecting an Input/Output Pad Directly to a Nonvolatile Memory Cell," filed Jul. 28, 1995 (assigned to the assignee of the present application).
Generation of the control signals needed for entry into each of the test modes of chip 203 is preferably accomplished in the manner described in the U.S. patent application Ser. No. 08/508,924, entitled "Memory System Having Internal State Monitoring Circuit," filed Jul. 28, 1995, and in U.S. patent application Ser. No. 08/386,704 entitled "Apparatus for Entering and Executing Test Mode Operations for Memory," filed Feb. 10, 1995. Control unit 29 of chip 203 can include circuitry for generating the control signals needed for entry into each test mode (in response to signals received at external pads of the chip), and circuitry for generating the control signals needed for controlling operation of the chip during execution of some test mode operations and for controlling operation of the chip in the normal operating mode.
With reference to FIG. 4, sense amplifier 19 is a differential amplifier. Circuit 14 couples the noninverting input of sense amplifier 19 to a selected column of array 16. Current source 119 holds the inverting input of sense amplifier 19 at reference voltage V.sub.REF and causes current I.sub.REF to flow to ground from the inverting input of sense amplifier 19.
Still with reference to FIG. 4, when memory chip 203 enters certain ones of its test modes (including the true V.sub.th measurement test mode), the level of at least one of control signals "VTH" and "VTL" asserted from control unit 29 to switch 121' goes high, and the level of control signal "Test Mode Enable 2" asserted from control unit 29 to switch 40 goes low. In response to such high level of at least one of VTH and VTL, switch 121' enters a closed (conductive) state in which it asserts voltage V.sub.sup from pad 90 to X decoder 12'. Voltage V.sub.sup can have any of a broad range of selected values, including values much greater than the supply voltage V.sub.cc of chip 203 and values much less than supply voltage V.sub.cc. In response to the low level of Test Mode Enable 2, switch 40 enters an "open" (non-conductive) state in which signals (indicative of data to be written to memory array 16) provided from an external device to I/O pad 30 are buffered in input buffer 18 and then asserted to memory array 16, or signals (indicative of data read from memory array 16) are asserted from memory array 16 to sense amplifier 19, and the output of sense amplifier 19 is buffered in output buffer 20 and asserted to I/O pad 30.
In other test modes of chip 203 (not including the true V.sub.th measurement test mode), the level of Test Mode Enable 2 is high, and switch 40 responds thereto by entering its "closed" (conductive) state in which it passes test signals indicative of test data to be written to or read from a selected cell or cells of array 16 (e.g., a current signal indicative of test data read from a selected cell). In such modes, buffers 18 and 20 are disabled and the test signals pass through switch 40 (and thus between I/O pad 30 and the selected cell or cells of array 16) without passing through buffer 10.
In the true V.sub.th measurement test mode of chip 203, control unit 29 asserts at least one of VTH and VTL with a high level to switch 121', to cause switch 121' to provide voltage V.sub.sup from pad 90 to X decoder 12'. As shown in FIG. 5, control unit 29 asserts control signals VTL and VTH, and also control signal HV.sub.-- CYC to switch 121'. Signal VTH has a high level (a logical "1") during the true V.sub.th measurement test mode when V.sub.sup is above the supply voltage V.sub.cc (e.g., when V.sub.cc is 5 volts, and V.sub.sup is 12 volts), and a low level (a logical "0") during the true V.sub.th measurement test mode when V.sub.sup is below supply voltage V.sub.cc. Also in the true V.sub.th measurement test mode, signal VTL has a high level when V.sub.sup is below the supply voltage V.sub.cc (e.g., when V.sub.cc is 5 volts, and V.sub.sup is 3 volts), and a low level when V.sub.sup is above supply voltage V.sub.cc.
Typically, control unit 29 asserts signal VTL with a high level (and V.sub.sup is less than V.sub.cc) during a process of determining threshold voltages (or threshold voltage distributions) of erased cells of array 16 in a true V.sub.th measurement test mode (since erased cells typically have threshold voltages substantially lower than V.sub.cc). Typically, control unit 29 asserts signal VTH with a high level (and V.sub.sup is greater than V.sub.cc) at some stages of a process of determining threshold voltages (or threshold voltage distributions) of programmed cells of array 16 in a true V.sub.th measurement test mode (since programmed cells typically have threshold voltages approximately equal to V.sub.cc).
During normal operation (i.e., non-test mode operation), signal HV.sub.-- CYC (which is also generated in control unit 29) goes high when high voltage operations are required, such as to program or erase cells of the memory array. Thus, control unit 29 asserts HV.sub.-- CYC with a high level to switch 121' to cause switch 121' to enter a closed state in which it provides voltage V.sub.sup from pad 90 to X decoder 12'.
U.S. patent application Ser. No. 08/508,923 entitled "Memory System Having Non-volatile Data Storage Structure for Memory Control Parameters and Method," filed by F. Roohparvar on Jul. 28, 1995 (assigned to the assignee of the present application) discloses a memory chip having circuitry for providing an internally generated adjustable reference voltage to a sense amplifier. The circuitry asserts a particular level of the reference voltage (one of a discrete set of possible reference voltages) in response to stored control bits read from non-volatile data storage units. The stored control bits can be programmed and reprogrammed at any time after fabrication of the chip in response to programming signals received at the chip from an external processor.
However, two limitations of the sense amplifier reference voltage selection circuitry of U.S. patent application Ser. No. 08/508,923 are: only a discrete set (rather than a continuous range) of reference voltages are available for the sense amplifier during a test mode, and the set of available reference voltages for the sense amplifier may be insufficiently broad to determine the characteristics of all the cells (with all combinations of voltages applied to the control gate and source of each cell) during a test mode.
The latter limitation can exist due to the small geometries that are typical in state of the art memory arrays, which causes the so-called "leaky column" problem often to be inherent in newly manufactured arrays, which in turn causes some cells to fail to turn off even if their control gate voltages are turned off (grounded). The "leaky column" problem causes an increased current on the column (the bitline) of each cell which fails to turn off when its control gate voltage is turned off. For example, when a programming operation has been performed to program one cell in a column and a selected voltage (e.g., 3 volts) is then applied to the cell's control gate (the selected voltage being above the threshold voltage of a typical erased cell and thus adequate to turn on a typical erased cell, but below the threshold voltage of a typical programmed cell and thus inadequate to turn on a typical programmed cell) and the other cells in the column are deselected, the current in the column may be higher than expected (due to unexpectedly high leakage). Thus: the programmed cell may incorrectly be interpreted as being in an erased state (during normal, non-test-mode operation); and it may not be possible fully to characterize the programmed cell (in a test mode in which the wordline voltage of the cell is swept or otherwise varied) unless a broad range of sense amplifier reference voltages (including reference voltages in a range lower and/or higher than typically employed to read and verify cells in normal, non-test-mode operation) are applied to the reference input terminal of the sense amplifier. The latter is true since the sense amplifier's output will change state only when the voltage at one input terminal (typically a noninverting input terminal) of the sense amplifier falls below (or rises above) the reference voltage at the sense amplifier's reference input terminal (typically an inverting input terminal). The internal reference voltage generation circuitry of the chip may be incapable of providing sufficiently high or low sense amplifier reference voltages (and corresponding sense amplifier reference currents) to characterize the cell, or the internal reference voltage generation circuitry of the chip may be incapable of providing a continuous range of sufficiently low (or high) sense amplifier reference voltages, where a continuous range of reference voltages rather than a set of discrete values thereof is needed to characterize the cell accurately.
The present invention enables implementation of test modes (including true V.sub.th measurement test modes) in which any of a broad range of sense amplifier reference voltages is applied directly from an external device to a reference input terminal of a sense amplifier of a memory chip, without the need for sense amplifier reference voltage selection circuitry (such as that disclosed in U.S. patent application Ser. No. 08/508,923) in the chip for implementing the test modes. The invention also enables implementation of test modes (including true V.sub.th measurement test modes) in which any of a continuous range of sense amplifier reference voltages is applied directly from an external device to a reference input terminal of a sense amplifier of a memory chip, rather than one of a set of discrete values of sense amplifier reference voltages as provided by the sense amplifier reference voltage selection circuitry of U.S. Ser. No. 08/508,923.